Novel method for dual-layer polyimide processing on bumping technology

ABSTRACT

A new method and processing sequence is provided for the formation of solder bumps that are in contact with underlying aluminum contact pads. A patterned layer of negative photoresist is interposed between a patterned layer of PE Si 3 N 4  and a patterned layer of polyamide insulator. The patterned negative photoresist partially overlays the aluminum contact pad and prevents contact between the layer of polyamide insulator and the aluminum contact pad. By forming this barrier no moisture that is contained in the polyamide insulator can come in contact with the aluminum contact pad, therefore no corrosion in the surface of the aluminum contact pad can occur.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The invention relates to the fabrication of integrated circuitdevices, and more particularly, to a method to create solder bumps forthe interconnection of semiconductor devices.

[0003] (2) Description of the Prior Art

[0004] Semiconductor technology has, ever since its inception, improvedsemiconductor device performance by reducing device dimensions and,concurrently, increasing device packaging density. In the field of highdensity interconnect technology, it is necessary for many of thepackaging approaches to fabricate a multilayer structure on a substratein order to connect integrated circuits to one another. To achieve ahigh wiring and packing density, many integrated circuit chips arephysically and electrically connected to a single substrate commonlyreferred to as a multi-chip module (MCM). Typically, layers of adielectric such as a polyimide separate metal power and ground planes inthe substrate. Embedded in other dielectric layers are metal conductorlines with vias (holes) providing electrical connections between signallines or to the metal power and ground planes.

[0005] The methods that are used to interconnect a semiconductor deviceto an underlying substrate can be differentiated in methods of wirebonding (device interconnect points are provided around the periphery ofthe device, a factor that limits the number of input/output connectionsthat can be made to the device), tape automatic bonding (deviceinterconnect points are provided around the periphery of the device,again limiting I/O capability) and C4 or Controlled Collapse ChipConnection methods. The latter method of C4 interconnect offers theadvantage of providing high input/output capability since theinterconnect bumps can be placed in any location on the chip. The C4technology offers, in addition to high I/O interconnect capacity, theadvantage of short solder bumps (improving the electrical performance ofthe interconnect) while the process of reflow that is used to connectthe solder bumps with the substrate allows the formation of aself-aligned interface between the solder bump and the contact point inthe substrate to which the solder bump is connected.

[0006] For the formation of solder bumps, two different and wellestablished technologies can be used, that is evaporation andelectroplating. Other methods that are used are methods of adhesiveapplying, stud-bumping methods and the like. These latter methods willnot be further discussed at this point.

[0007] The method of electroplating follows the processing steps of(over the surface of a substrate wherein a point of electrical contact,typically containing aluminum, has been provided, all steps ofprocessing being centered around this point of electrical contact)depositing a layer of polyimide and etching an opening in this layer ofpolyimide that aligns with the point of contact, depositing (by vacuumevaporation) a layer of Under Bump Metallurgy (UBM, also referred to asBall Limiting Metallurgy or BLM) over the layer of poly including theopening created in the layer of poly. A layer of photoresist isdeposited over the layer of UBM and patterned, creating an opening inthe layer of photoresist that aligns with that part of the layer of UBMthat remains in place under the to be created solder bump. Next a layerof metal (typically copper) is electroplated over the layer ofphotoresist whereby the layer of UBM serves as the common electrode forthe electroplating process, the electroplated metal is in contact withthe layer of UBM. A layer of solder is next plated over the layer ofelectroplated metal. The layer of electroplated metal is centered aroundthe opening that has been created in the layer of photoresist as is thelayer of plated solder. The photoresist is removed using the solder bumpas a mask, the layer of UBM is selectively etched and removed where thislayer does not underlie the to be created solder bump in order toelectrically isolate the solder bumps from each other. A critical stepof the process is performed as a final step whereby a flux is applied tothe plated solder and the solder is melted in a reflow furnace under anitrogen atmosphere, creating a spherically shaped solder bump. Theabove summarized processing steps of electroplating that are used forthe creation of a solder bump can be supplemented by the step of curingor pre-baking of the layer of photoresist after this layer has beendeposited over the layer of UBM.

[0008] The process of evaporation also starts with a semiconductorsurface wherein a metal point of contact has been provided. A layer ofpassivation is deposited and patterned, creating an opening in the layerof passivation that aligns with the metal point of contact. A layer ofUBM is formed over the layer of passivation and inside the openingcreated in the layer of passivation. The UBM layer may be a compositelayer of metal such as chromium followed by copper followed by gold inorder to promote (with the chromium) improved adhesion of the UBM layerand to form a diffusion barrier layer or to prevent oxidation (with thegold over the copper). Solder is next selectively plated over thedeposited layer of UBM and melted in a solder reflow surface in ahydrogen ambient for solder reflow, in this manner forming thespherically shaped solder bumps.

[0009] Some of the problems that have over time been experienced usingthe various processes are:

[0010] electroplating suffers from the problem that the etching of thelayer of UBM may affect the solder that has been deposited since thissolder is readily attacked by an acid solution; any acid that is usedfor the etching of the layer of UBM may adversely affect the depositedsolder

[0011] the previous problem of the solder being affected during the UBMetch can be reduced by the application of a second mask that protectsthe deposited solder during the UBM etch; this however adds complexityand expense to the process of the formation of solder bumps while theadditional mask complicates the processing sequence

[0012] the polyimide that is used during the electroplating procedure isdifficult to completely remove from the opening that is etched in thelayer of poly that aligns with the point of electrical contact; thiscreates a poorly defined opening in the layer of poly, which in turnresults in a low quality contact between the solder bump and theunderlying point of electrical contact

[0013] the process of electroplating is relatively complex and requiresa significant number of processing steps

[0014] the process of evaporation is generally more expensive than theprocess of electroplating, and

[0015] the process of evaporation is, for decreased device dimensions,more difficult to control and therefore does not lend itself well to theera of sub-micron devices.

[0016] The present invention addresses concerns of the prior art methodof forming solder bumps on a semiconductor surface. This prior artmethod is highlighted in FIG. 1, which contains the followingsub-components:

[0017]10 is a semiconductor surface on which the solder bump is to becreated

[0018]12 is the metal contact pad, typically containing aluminum, whichis to be brought into contact with the solder bump and over which thesolder bump therefore is to be created

[0019]14 is a patterned layer of Plasma Enhanced silicon nitride whichserves as an etch stop layer for the etch of the overlying layer

[0020]16 of insulation that contains polyamide (a polyamide insulator orPI coating)

[0021]18 is a layer of Under Bump Metallurgy (UBM), and

[0022]20 is the created solder bump. The prior art processing sequencefor the formation of the solder bump that is shown in FIG. 1 is asfollows:

[0023] depositing a layer of PE Si₃N₄ over the semiconductor surface 10thereby including the surface of the aluminum pad 12

[0024] patterning and etching the deposited layer of PE Si₃N₄, creatingan opening in the layer of PE Si₃N₄ that aligns with the aluminum pad 12

[0025] applying a coating 16 of polyamide insulator (PT) over thesurface of the layer 14 of PE Si₃N₄ including the exposed surface of thealuminum contact pad 12

[0026] patterning and etching the layer 16 of PT, creating an opening inthe layer 16 of PI that aligns with the aluminum pad 12

[0027] curing the etched layer 16 of PI

[0028] depositing a layer 18 of Under Bump Metallurgy (UBM) over thesurface of the etched and cured layer 16 of PI

[0029] selectively depositing a layer (not shown in FIG. 1) of Pb/Sn toform solder bumps

[0030] selectively etching the deposited layer 18 of UBM to electricallyisolate the solder bumps from each other using the deposited layer ofPb/Sn as a mask, and

[0031] melting the selectively deposited Pb/Sn in a reflow furnacecreating the spherically shaped solder bump 20.

[0032] The problem areas that appear as part of the prior art processingsequence that is shown in FIG. 1 are the regions 22. Layer 16 ofpolyamide insulator is used for isolation and for planarization duringthe processing sequence of forming solder bumps. Polyamide however isprone to water absorption, the layer 16 is in contact with the aluminumpad 12 in regions 22. Even minute traces of water that are present inthe layer 16 of polyamide insulator causes corrosion of the surface ofthe aluminum pad 12 in regions 22, resulting in poor adhesion betweenthe layer 16 of polyamide insulator and the aluminum pad 12.

[0033] U.S. Pat. No. 5,946,590 (Satoh) shows a bump process using 2organic layers for plating.

[0034] U.S. Pat. No. 5,492,235 (Crafts et al.) shows a bump creationprocess using UBM, and creating the bump by evaporation.

[0035] U.S. Pat. No. 5,903,058 (Akram) and U.S. Pat. No. 6,028,011(Takase et al.) show other related bump processes.

SUMMARY OF THE INVENTION

[0036] A principle objective of the invention is to create a solder bumpwhereby no corrosion occurs in the surface of the aluminum contact padto which the solder bump is connected.

[0037] Another objective of the invention is to provide improvedadhesion between the structure of the solder bump and the underlyingcontact pad of aluminum by creating a layer of negative photoresist thatis in contact with a portion of the surface of the underlying aluminumcontact pad.

[0038] Yet another objective of the invention is to provide a methodthat improves the insulation of an aluminum contact pad and the regionsthat are adjacent to the aluminum contact pad.

[0039] In accordance with the objectives of the invention a new methodand processing sequence is provided for the formation of solder bumpsthat are in contact with underlying aluminum contact pads. Using theprocess of the invention, a patterned layer of negative photoresist isinterposed between a patterned layer of PE Si₃N₄ and a patterned layerof polyamide insulator. The patterned negative photoresist partiallyoverlays the aluminum contact pad and prevents contact (that was createdusing the prior art processing sequence) between the layer of polyamideinsulator and the aluminum contact pad. By forming this barrier (betweenthe polyamide insulator and the aluminum contact pad) no moisture thatis contained in the polyamide insulator can come in contact with thealuminum contact pad, therefore no corrosion in the surface of thealuminum contact pad will occur.

BRIEF DESCRIPTION OF THE DRAWINGS

[0040]FIG. 1 shows a cross section and the therefrom followingprocessing flow of the creation of a prior art solder bump.

[0041]FIG. 2 shows a cross section and the therefrom followingprocessing flow of the creation of a solder bump of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] It must be noted that the use of polyimide films as inter-leveldielectrics has been pursued as a technique for providing partialplanarization of a dielectric surface. Polyimides offer the followingcharacteristics for such applications:

[0043] they produce surfaces in which the step height of underlyingfeatures is reduced, step slopes are gentle and smooth

[0044] they are available to fill small openings without producing thevoids that occur when low-temperature CVD oxide films are deposited

[0045] cured polyimide films can tolerate temperatures of up to 500degrees C. without degradation of their dielectric film characteristics

[0046] polyimide films have dielectric breakdowns which are onlyslightly lower than that of SiO₂

[0047] the dielectric constant of polyimides is smaller than that ofsilicon nitride and of SiO₂

[0048] the process used to deposit and pattern polyimide films isrelatively simple.

[0049] A layer of polyimide can be deposited by spin-on coating and canbe cured after deposition at for instance 400 degrees C. for 1 hour in avacuum or nitrogen ambient.

[0050] Referring now specifically to FIG. 2, there is shown a crosssection of the formation of a solder bump using the process of theinvention.

[0051] Layer 10 is the surface of a semiconductor layer, a contact pad12 has been created on surface 10. Surface 10 will typically be thesurface of a semiconductor substrate, the surface of an interconnectsubstrate and the like. The essence of surface 10 is that a contact pad12 has been created on this surface, electrical contact must beestablished with contact pad 12 by means of an overlying solder bump.Contact pad 12 therefore serves as interface between the solder bump andelectrical interconnects that are provided in the surface of layer 10.

[0052] A layer 14 of Plasma Enhanced silicon nitride (PE Si₃N₄) isdeposited over the surface of layer 10 and of contact pad 12.

[0053] Insulating layers such as silicon oxide and oxygen-containingpolymers are deposited over the surface of various layers of conductinglines in a semiconductor device or substrate to separated the conductiveinterconnect lines from each other, the insulating layers can bedeposited using Chemical Vapor Deposition (CVD) techniques. Theinsulating layers are deposited over patterned layers of interconnectinglines where electrical contact between successive layers ofinterconnecting lines is established with metal vias created for thispurpose in the insulating layers. Electrical contact to the chip istypically established by means of bonding pads or contact pads that formelectrical interfaces with patterned levels of interconnecting metallines. Signal lines and power/ground lines can be connected to thebonding pads or contact pads. After the bonding pads or contact padshave been created on the surfaces of the chip package, the bonding padsor contact pads are passivated and electrically insulated by thedeposition of a passivation layer over the surface of the bonding pads.A passivation layer can contain silicon oxide/silicon nitride(SiO₂/Si₃N₄) deposited by CVD. The passivation layer is patterned andetched to create openings in the passivation layer for the bonding padsor contact pads after which a second and relatively thick passivationlayer can be deposited that further insulation and protection of thesurface of the chips from moisture and other contaminants and frommechanical damage during assembling of the chips.

[0054] Various materials have found application in the creation ofpassivation layers. Passivation layer can contain silicon oxide/siliconnitride (SiO₂/Si₃N₄) deposited by CVD, passivation layer can be aphotosensitive polyimide or can comprise titanium nitride. Anothermaterial often used for passivation layer is phosphorous doped silicondioxide that is typically deposited over a final layer of aluminuminterconnect using a Low Temperature CVD process. In recent years,photosensitive polyimide has frequently been used for the creation ofpassivation layers. Conventional polyimides have a number of attractivecharacteristics for their application in a semiconductor devicestructure, which have been highlighted above. Photosensitive polyimideshave these same characteristics but can, in addition, be patterned likea photoresist mask and can, after patterning and etching, remain on thesurface on which it has been deposited to serve as a passivation layer.Typically and to improve surface adhesion and tension reduction, aprecursor layer is first deposited by, for example, conventionalphotoresist spin coating. The precursor is, after a low temperaturepre-bake, exposed using, for example, a step and repeat projectionaligner and Ultra Violet (UV) light as a light source. The portions ofthe precursor that have been exposed in this manner are cross linkedthereby leaving unexposed regions (that are not cross linked) over thebonding pads. During subsequent development, the unexposed polyimideprecursor layer (over the bonding pads) is dissolved thereby providingopenings over the bonding pads. A final step of thermal curing leaves apermanent high quality passivation layer of polyimide over thesubstrate.

[0055] The preferred material of the invention for the deposition oflayer 14 of passivation is Plasma Enhanced silicon nitride (PE Si₃N₄),deposited using PECVD technology at a temperature between about 350 and450 degrees C. with a pressure of between about 2.0 and 2.8 Torr for theduration between about 8 and 12 seconds. Layer 14 of PE Si₃N₄ can bedeposited to a thickness between about 200 and 800 Angstrom.

[0056] Layer 14 of PE Si₃N₄ is next patterned and etched to create anopening in the layer 14 that overlays and aligns with the underlyingcontact pad 12.

[0057] The etching of layer 14 can use Ar/CF₄ as an etchant at atemperature of between about 120 and 160 degrees C. and a pressure ofbetween about 0.30 and 0.40 Torr for a time of between about 33 and 39seconds using a dry etch process.

[0058] The etching of layer 14 can also use He/NF₃ as an etchant at atemperature of between about 80 and 100 degrees C. and a pressure ofbetween about 1.20 and 1.30 Torr for a time of between about 20 and 30seconds using a dry etch process.

[0059] A layer 15 of negative photoresist is next deposited over thesurface of the layer 14 of PE Si₃N₄. The layer 15 of photoresist can bedeposited to a thickness of between about 300 and 800 Angstrom.

[0060] The methods used for the deposition and development of the layer15 of negative photoresist uses conventional methods ofphotolithography. Photolithography is a common approach whereinpatterned layers are usually formed by spinning on a layer ofphotoresist, projecting light through a photomask with the desiredpattern onto the photoresist to expose the photoresist to the pattern,developing the photoresist, washing off the undeveloped photoresist, andplasma etching to clean out the areas where the photoresist has beenwashed away. The exposed resist may be rendered insoluble(positive-working) and form the pattern, or insoluble (negative working)and be washed away.

[0061] Before layer 15 of negative photoresist is patterned and etched,a layer 16 of polyamide insulator is deposited over the surface of thelayer 15 of negative photoresist. Layer 16 can be deposited usingmethods of spin-on coating whereby this layer 16 of PI can be depositedto a thickness between about 300 and 800 Angstrom.

[0062] The layer 15 of negative photoresist will, upon patterning andetching, remain in place over the surface of pad 12 in an area that hasthe shape of the perimeter of the aluminum pad 12 and that is slightlyremoved from this perimeter toward the center of pad 12. Negativephotoresist will, upon exposure to UV light, harden which is a qualitythat may be of value in selectively creating a firmer layer 15 ofnegative photoresist overlying the contact pad 12.

[0063] After both layers 15 (of negative photoresist) and 16 (of PT)have been deposited, both layers are patterned and etched forming astacked layer of negative photoresist and PI overlying the aluminum pad12.

[0064] Polyamide insulating layer 16 can be anisotropically etched witha plasma gas containing carbon tetrofluoride (CF₄) as an etchant using acommercially available parallel plate RIE etcher or an ElectronCyclotron Resonance (ECR) plasma reactor. The preferred processingconditions for the etching of insulating layer 16 are as follows:etchant used: CF₄/CHF₃, flow rate about 25 sccm, temperature about 40degrees C., pressure about 225 mTorr, time of the etch between about 160and 220 seconds.

[0065] Layer 15 of negative photoresist can be etched by applying O₂plasma and then wet stripping by using H₂SO₄, H₂O₂ and NH₄OH solution.Sulfuric acid (H₂SO₄) and mixtures of H₂SO₄ with other oxidizing agentssuch as hydrogen peroxide (H₂O₂) are widely used in strippingphotoresist after the photoresist has been stripped by other means.Wafers to be stripped can be immersed in the mixture at a temperaturebetween about 100 degrees C. and about 150 degrees C. for 5 to 10minutes and then subjected to a thorough cleaning with deionized waterand dried by dry nitrogen. Inorganic resist strippers, such as thesulfuric acid mixtures, are very effective in the residual free removalof highly postbaked resist. They are more effective than organicstrippers and the longer the immersion time, the cleaner and moreresidue free wafer surface can be obtained.

[0066] The photoresist layer 15 can also be partially removed usingplasma oxygen ashing and careful wet clean. The oxygen plasma ashing isheating the photoresist in a highly oxidized environment, such as anoxygen plasma, thereby converting the photoresist to an easily removedash. The oxygen plasma ashing can be followed by a native oxide dip for90 seconds in a 200:1 diluted solution of hydrofluoric acid.

[0067] After the two layers 15 (photoresist) and 16 (PI) have beenpatterned and etched, both layers are cured. The curing andcross-linking of layers 15 and 16 provides extra protection to thedevice circuitry and can be performed in a N₂ gas ambient at atemperature of between about 300 and 400 degrees C. for a time periodbetween about 1.5 and 2.5 hours and a pressure of 760 Torr.

[0068] At this point in the processing sequence, there exist two layers,that is a layer of patterned negative photoresist (layer 15) and a layerof PI (layer 16), both layers overlying the patterned layer 14 of PESi₃N₄, both layers 15 and 16 have been cured and an opening has beencreated through both layers over which the solder ball must be formed.The process is, at this point, ready to create the UBM layer and thesolder bump.

[0069] The next step in the process of the invention is therefore thecreation of the layer 18 of UBM by vacuum evaporation, this layer is asyet to be patterned and etched. The surface of layer 18 of UBM is, afterits blanket deposition and before patterning of the layer of UBM,selectively plated with solder. This solder plating is aligned with thealuminum pad 12. UBM layer 18 is then etched using the plated solder asa mask. This removes the layer of UBM from areas adjacent to the contactpad 12 and leaves only enough of the UBM in place to form an electricalinterface between the solder bump and the contact pad 12. Standard RIEprocedures, using Cl₂—BCl₃ as etchant, can be used to etch the UBM layer18.

[0070] A flux is next applied to the selectively plated solder and thesolder is melted in a reflow surface under a nitrogen atmosphere,forming the spherically shaped solder bump 20 that is shown in FIG. 2.

[0071] It is clear from FIG. 2 that the surface of the aluminum pad 12that underlies the layer 16 of polyamide insulator is separated fromlayer 16 by a layer 15 of negative photoresist. This separation preventsany moisture that is present in the layer 16 from coming in contact withthe aluminum pad 12, thus preventing any corrosion of the surface of thealuminum pad 12.

[0072] The process of the invention can be summarized as follows:

[0073] deposit a layer of PE SiN over the semiconductor surface,including the surface of the aluminum pad

[0074] pattern the deposited layer of PE SiN forming an opening with afirst diameter in the layer of PE SiN that aligns with the aluminum pad,partially exposing the surface of the aluminum pad

[0075] apply a coating of negative photoresist over the patterned layerof PE SiN, including the exposed surface of the aluminum pad

[0076] apply a coating of polyamine insulator over the surface of thenegative photoresist

[0077] pattern and etch the layers of photoresist and polyamineinsulator, forming a stack of photoresist and polyamine overlying thesemiconductor surface while forming an opening with a second diameterthrough both layers that aligns with the aluminum pad; the above seconddiameter is smaller than the above first diameter, resulting in thenegative photoresist partially overlying the surface of the aluminum padand forming an interface between the aluminum pad and the layer ofpolyamide

[0078] curing the layers of photoresist and polyamine insulator

[0079] depositing a layer of UBM over the surface of the layer ofpolyamine insulator, the layer of UBM is in electrical contact with thealuminum pad

[0080] selectively depositing solder over the surface of the layer ofUBM, the solder deposition is aligned with the underlying aluminum pad

[0081] etching the layer of UBM using the deposited solder as a mask,thus preventing electrical shorts between layers of UBM that are formedfor different solder bumps

[0082] applying a flux or paste to the solder, and

[0083] flowing the solder, forming the solder bump.

[0084] Although the invention has been described and illustrated withreference to specific illustrative embodiments thereof, it is notintended that the invention be limited to those illustrativeembodiments. Those skilled in the art will recognize that variations andmodifications can be made without departing from the spirit of theinvention. It is therefore intended to include within the invention allsuch variations and modifications which fall within the scope of theappended claims and equivalents thereof.

What is claimed is:
 1. A method for forming a bump on a semiconductorsurface, a contact pad having been provided on said semiconductorsurface, comprising: depositing a layer of passivation over saidsemiconductor surface including the surface of said contact pad;patterning and etching said layer of passivation creating an opening insaid layer of passivation having a first diameter, partially firstexposing the surface of said contact pad over a surface area of saidfirst diameter; depositing a layer of negative photoresist over thesurface of said layer of passivation, including said partially firstexposed surface of said contact pad; depositing a layer of polyimideover the surface of said layer of negative photoresist; patterning andetching said layer of polyimide and said layer of negative photoresist,creating an opening in said layers of polyimide and of negativephotoresist having a second diameter whereby said second diameter issmaller than said first diameter by a measurable amount, partiallysecond exposing the surface of said contact pad over a surface area ofsaid second diameter; curing said layer of polyimide and said layer ofnegative photoresist; blanket plating a layer of Under Bump Metallurgy(UBM) over the surface of said layer of polyimide, including saidpartially second exposed surface of said contact pad over a surface areaof said second diameter; selectively plating the surface of said layerof UBM with a layer of solder, said layer of solder overlying saidcontact pad; etching said layer of UBM, using said selectively platedlayer of solder as a mask, removing said layer of UBM from the surfaceof said layer of polyimide over which no solder has been plated;applying a flux to said layer of solder; and flowing said layer ofsolder forming said solder bump.
 2. The method of claim 1 wherein saidlayer of passivation comprises PE Si₃N₄ deposited to a thickness betweenabout 200 and 800 Angstrom.
 3. The method of claim 1 wherein said layerof passivation is selected from the group comprising the materials PESi₃N₄, SiO₂, a photosensitive polyimide, phosphorous doped silicondioxide and titanium nitride deposited to a thickness between about 200and 800 Angstrom.
 4. The method of claim 1 wherein said layer ofpolyimide comprises polyamide insulator deposited to a thickness betweenabout 300 and 800 Angstrom.
 5. The method of claim 1 wherein said layerof Under Bump Metallurgy comprises a layer of chromium followed by alayer of copper followed by a layer of gold.
 6. The method of claim 1wherein said curing said layer of polyimide and said layer of negativephotoresist is performed in a N₂ gas ambient at a temperature of betweenabout 300 and 400 degrees C. for a time period between about 1.5 and 2.5hours and a pressure of 760 Torr.
 7. The method of claim 1 wherein saidpassivation layer deposited over the surface of said semiconductorsurface comprises a plurality of superimposed passivation layers.
 8. Themethod of claim 7 wherein at least one of said plurality of superimposedpassivation layers is selected from a group containing PE Si₃N₄, SiO₂, aphotosensitive polyimide, phosphorous doped silicon dioxide and titaniumnitride.
 9. The method of claim 1 wherein said layer of Under BumpMetallurgy comprises a plurality of sub-layers of different metalliccomposition.
 10. The method of claim 1 wherein said contact pad on saidsemiconductor surface is electrically connected with a semiconductordevice with a least one conductive line of interconnect or with at leastone conductive contact point.
 11. The method of claim 1 wherein saidetching said layer of UBM comprises sputter etching or wet etching. 12.A conductive bump overlying a layer of Under Bump Metallization (UBM)formed in electrical contact with at least one contact pad underlying atleast one via defined in three superimposed layers of at least one layerof passivation deposited over a semiconductor substrate, at least onelayer of negative photoresist deposited over said layer of passivationand at least one layer of polyimide deposited over said layer ofnegative photoresist, comprising: providing said semiconductor substrateincluding integrated circuitry therein, and at least one layer ofpassivation having a thickness deposited over thee surface of saidsemiconductor substrate, with at least one contact pad having beenprovided in the surface of said substrate; providing access to saidintegrated circuit for external contact by forming at least one firstvia having a first diameter extending through said at least one layer ofpassivation, said at least one first via being aligned with said atleast one contact pad in the surface of said substrate; providing atleast one layer of negative photoresist deposited over said at least onelayer of passivation, further providing at least one layer of polyimidedeposited over the surface of said at least one layer of negativephotoresist; providing access to said integrated circuit for externalcontact by forming at least one second via having a second diameterextending through said at least one layer of polyimide further extendingthrough said at least one layer of negative photoresist, said seconddiameter being smaller than said first diameter by a measurable amount,said second via further being aligned with said first via; curing saidat least one layer of polyimide and said at least one layer of negativephotoresist; forming a substantially conformal layer of UBM metal havinga thickness over said at least one layer of polyimide with a portion ofsaid metal layer extending into said at least one second via furtherextending into said at least one first via to make electrical contactwith said integrated circuit; selectively plating a layer of Pb/Sn oversaid layer of metal, said selectively plated layer of Pb/Sn beingaligned with said at least one second via; selectively removing said UBMmetal layer from the surface of said at least one layer of polyimide,using said selectively plated layer of Pb/Sn as a mask, creating UBMlayers of said metal that are aligned with said second via; selectivelydepositing paste or flux over the surface of said selectively platedlayer of Pb/Sn; and flowing said selectively plated layer of Pb/Sn,forming said conductive bump overlying a layer of Under BumpMetallization.
 13. The conductive bump of claim 12 wherein said at leastone layer of passivation comprises PE Si₃N₄ deposited to a thicknessbetween about 200 and 800 Angstrom.
 14. The conductive bump of claim 12wherein said at least one of said at least one layer of passivation isselected from the group comprising the materials PE Si₃N₄, SiO₂, aphotosensitive polyimide, phosphorous doped silicon dioxide and titaniumnitride deposited to a thickness between about 200 and 800 Angstrom. 15.The conductive bump of claim 12 wherein said at least one layer ofpolyimide comprises polyamide insulator deposited to a thickness betweenabout 300 and 800 Angstrom.
 16. The conductive bump of claim 12 whereinsaid layer of Under Bump Metallurgy comprises a layer of chromiumfollowed by a layer of copper followed by a layer of gold.
 17. Theconductive bump of claim 12 wherein said curing of said at least onelayer of polyimide and said at least one layer of negative photoresistis performed in a N₂ gas ambient at a temperature of between about 300and 400 degrees C. for a time period between about 1.5 and 2.5 hours anda pressure of 760 Torr.
 18. The conductive bump of claim 12 wherein saidlayer of Under Bump Metallurgy comprises a plurality of sub-layers ofdifferent metallic composition.
 19. The conductive bump of claim 12wherein said contact pad on said semiconductor surface is electricallyconnected with a semiconductor device with a least one conductive lineof interconnect or with at least one conductive contact point.
 20. Theconductive bump of claim 12 wherein said removing said UBM metal layerfrom the surface of said at least one layer of polyimide comprisessputter etching or wet etching.
 21. A method for forming a bump on asemiconductor surface, a contact pad having been provided on saidsemiconductor surface, comprising: depositing one or more layers of PESi₃N₄ over said semiconductor surface including the surface of saidcontact pad, deposited to a thickness between about 200 and 800Angstrom; patterning and etching said one or more layers of PE Si₃N₄creating a via opening in said one or more layers of PE Si₃N₄ having afirst diameter, partially first exposing the surface of said contact padover a surface area of said first diameter; depositing a layer ofnegative photoresist over the surface of said layer of PE Si₃N₄,including said partially first exposed surface of said contact pad;depositing a layer of polyamide insulator over the surface of said layerof negative photoresist, deposited to a thickness between about 300 and800 Angstrom; patterning and etching said layer of polyamide insulatorand said layer of negative photoresist, creating an opening in saidlayers of polyamide insulator and of negative photoresist having asecond diameter whereby said second diameter is smaller than said firstdiameter by a measurable amount, partially second exposing the surfaceof said contact pad over a surface area of said second diameter; curingsaid layer of polyamide insulator and said layer of negativephotoresist, in a N₂ gas ambient at a temperature of between about 300and 400 degrees C. for a time period between about 1.5 and 2.5 hours anda pressure of 760 Torr; blanket plating a layer of Under Bump Metallurgy(UBM) over the surface of said layer of polyamide insulator, includingsaid partially second exposed surface of said contact pad over a surfacearea of said second diameter, said layer of Under Bump Metallurgycomprising one or more layers of different metallic composition;selectively plating the surface of said layer of UBM with a layer ofsolder, said layer of solder overlying said contact pad over a surfacearea of said second diameter; etching said layer of UBM, using saidselectively plated layer of solder as a mask, removing said layer of UBMfrom the surface of said layer of polyamide insulator over which nosolder has been plated, said etching of said layer of UBM comprisingsputter etching or wet etching; applying a flux to said layer of solder;and flowing said layer of solder forming said solder bump.
 22. Aconductive bump formed on a semiconductor surface, overlying a layer ofUnder Bump Metallization (UBM) formed in electrical contact with atleast contact pad underlying at least one via defined in threesuperimposed layers of at least one layer of passivation deposited overa semiconductor substrate, at least one layer of negative photoresistdeposited over said layer of passivation and at least one layer ofpolyimide deposited over said layer of negative photoresist, comprising:providing said semiconductor surface including integrated circuitrytherein, and at least one layer of passivation having a thicknessdeposited over said semiconductor substrate, said at least one layer ofpassivation comprising PE Si₃N₄ having been deposited to a thicknessbetween about 200 and 800 Angstrom; providing access to said integratedcircuitry for external contact by forming at least one first via havinga first diameter extending through said at least one layer ofpassivation; providing at least one layer of negative photoresistdeposited over said at least one layer of passivation, further providingat least one layer of polyamide insulator deposited over the surface ofsaid at least one layer of negative photoresist, said layer of at leastone layer of polyamide insulator deposited to a thickness between about300 and 800 Angstrom; providing access to said integrated circuitry forexternal contact by forming at least one second via having a seconddiameter extending through said at least one layer of polyamideinsulator further extending through said at least one layer of negativephotoresist, said second diameter being smaller than said first diameterby a measurable amount, said second via further being aligned with saidfirst via; curing said at least one layer of polyamide insulator andsaid at least one layer of negative photoresist in a N₂ gas ambient at atemperature of between about 300 and 400 degrees C. for a time periodbetween about 1.5 and 2.5 hours and a pressure of 760 Torr; forming asubstantially conformal layer of URM metal having a thickness over saidat least one layer of polyamide insulator with a portion of said metallayer extending into said at least one second via further extending intosaid at least one first via to make electrical contact with saidintegrated circuit, said layer of UBM comprising one or more layers ofdifferent metallic composition; selectively plating a layer of Pb/Snover said layer of metal, said selectively plated layer of Pb/Sn beingaligned with said at least one second via; selectively removing said UBMmetal layer from the surface of said at least one layer of polyamideinsulator, using said selectively plated layer of Pb/Sn as a mask,creating UBM layers of said metal that are aligned with said second via;selectively depositing paste or flux over the surface of saidselectively plated layer of Pb/Sn; and flowing said plated layer ofPb/Sn, forming said conductive bump overlying a layer of Under BumpMetallization.
 23. The method of claim 1 wherein said semiconductorsurface is selected from a group of surfaces comprising semiconductorsubstrates, printed circuit boards, flex circuits or a metallized orglass substrate or semiconductor device mounting support.
 24. The methodof claim 22 wherein said semiconductor surface is selected from a groupof surfaces comprising semiconductor substrates, printed circuit boards,flex circuits or a metallized or glass substrate or semiconductor devicemounting support.